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Area tradeoffs in a 3D Programmable Structured ASIC

conference contribution
posted on 2024-11-03, 13:39 authored by Norhazlin Khairudin, Justin Spangaro, Paul BeckettPaul Beckett
A major obstacle to the uptake of advanced fabrication nodes by small industry is high NRE costs, mainly due to initial mask generation. The Programmable Structured ASIC (psASIC) is intended to bridge the gap between FPGA and Structured ASIC approaches to application design. The psASIC prototype environment comprises a pair of stacked chips, one containing only logic and the other comprising only interconnect and configuration RAM. Once an application has been prototyped and debugged, the interconnect layer can be replaced with a set of semi-standardized metallization masks in a way that preserves the critical timing paths of the prototype. We analyze the tradeoffs between vertical interconnect density and logic size in the psASIC using a 130nm 3D process as an example.

History

Number

7575053

Start page

145

End page

148

Total pages

4

Outlet

Proceedings of the IEEE Symposium on Computer Applications & Industrial Electronics (ISCAIE 2016)

Name of conference

ISCAIE 2016

Publisher

IEEE

Place published

United States

Start date

2016-05-30

End date

2016-05-31

Language

English

Copyright

© 2016 IEEE.

Former Identifier

2006106851

Esploro creation date

2022-02-25

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