Design and simulation of a high performance rail-to-rail cmos op-amp at ±3v supply

The paper discusses a CMOS operational amplifier at ± 3 V supply, with rail-to-rail input and output performance. The trade-off between rail-to-rail performance and power consumption, in terms of bias current is observed. Simulation results with SPICE Level 3 models, using Cadence tools, are discussed and compared with other op-amps. The proposed circuit exhibits high speed with Slew Rate of 49.24 V/µs, better rejection ratios and offset performance, and consumes a power of 25.44 mW for rail-to-rail performance. The paper also discusses the effects of reducing the bias current to reduce power consumption.