Design techniques for NCL-based asynchronous circuits on commercial FPGA

While asynchronous techniques are of increasing interest in low-power design, designers cannot simply transfer current synchronous techniques to that domain. In particular, commercial FPGA systems and their accompanying EDA tools are not well suited to asynchronous logic design. In this paper we describe and analyze five alternative description methods that allow Null Convention Logic (NCL) based Asynchronous Circuits to be mapped to a commercial FPGA using the Verilog hardware description language and standard FPGA design tools. The techniques enable simple but robust NCL circuits to be developed using conventional methodologies.