Electron spin qubit transport and fault-tolerant architectures for Si:P quantum computing

Solid state quantum computer architectures are often touted as inherently scalable on the basis of proven classical architecture miniaturisation - i.e. through sheer ease of component replication. However, this weak scaling argument misses the vast complexity of the implementation of fault-tolerant quantum protocols required to protect quantum information processing against errors. In a successful design of strongly scalable quantum computer architecture, highly non-trivial requirements such as qubit transport, logic gates for physically separated qubits, fast read-out and resources for classical processing and error correction must be incorporated. We review a new adiabatic scheme coherent (spin) transport by adiabatic passage (CTAP) for physical qubit transport particularly suited to atomic and solid-state systems. The tunnelling rates, transfer times and the effects of decoherence are calculated for CTAP using phosphorous donors in silicon. Using CTAP qubit transport we have proposed a bi-linear donor electron spin architecture with potential for scale-up to fault-tolerant operation. This architecture allows for the distribution of interaction, storage and readout regions and incorporates non-nearest-neighbour interactions between qubits. The transport rails which provide these non-local interactions, also provide alternative pathways to avoid non-functioning regions. The key questions under investigation are whether one can: perform fault-tolerant quantum computation on such an architecture, and determine quantitative estimates of the fault-tolerant threshold.