FPGA Based Implementation and Area Performance Analysis of Sigma-Delta Modulated Steepest Algorithm for Channel Equalization

FPGA is now a common approach for implementing a wide range of DSP systems from simple to complex. Sigma-delta modulation (SDM) technique in combination with short word-length systems is attractive for almost all DSP applications. In this work, we design an adaptive channel equalizer on MATLAB and FPGA using sigma-delta modulation techniques to implement an improved steepest descent algorithm. Further, for functional validation and area performance analysis, the design is compared with its corresponding multi-bit implementation. The area-performance analysis validates the SDM as a useful technique for word length reduction.