Implementation of a short word length ternary FIR filter in both FPGA and ASIC

Despite the fact that Short Word Length (SWL) technique has been demonstrated to be a new efficient approach for implementing DSP systems, its applications are somehow limited. In this paper, we present the design and implementation of a Sigma-delta modulator based SWL ternary FIR filter. From predefined specifications, the filter was first modelled and simulated in MATLAB then implemented on a commercial FPGA platform and finally synthesized using ASIC method. We created two versions of the design: pipeline and non-pipeline, their performance are compared and discussed going from the operating frequency to the hardware resource usage. Also, to examine the trade-off between hardware efficiency and performance, we also evaluated the design with four different oversampling rates (8, 16, 32, 64).