Performance analysis of a logarithmic based phase detector for tan-locked loops

Nonlinear system design is a common practice in communication engineering for improved performances in advanced receivers. Here we look into a logarithmic based nonlinear loop for a second order arctan based digital phase locked loop (DPLL) for frequency synchronisation. The steady state and the acquisition performances of the loop are analyzed. The logarithmic nonlinearity is intentionally introduced to have improved phase noise performances during the steady state tracking mode. We present a close form expression for the open loop statistical distribution of the phase noise process and compare it with the linear PLL model on its performances. We also study the acquisition process of the loop by looking at the phase plane trajectories.