A Signal Conditioning Antiwindup Approach for Digital Stationary Frame Current Regulators

AC current regulators are susceptible to controller windup, i.e., the condition in which the controller dynamic states ramp the controller output up to very large values when the commanded reference cannot be achieved because of inverter saturation. Recovering from saturation can take considerable time once the linear mode has been restored, which degrades the current regulator's transient performance and can also impact on its stability. This paper proposes an improved formulation using the concept of signal conditioning, where windup is avoided by feeding the controller states entirely from the constrained inverter pulsewidth modulation command. Unlike previous approaches, this technique has the benefit of a simplified realization, since the controller transfer functions do not require algebraic reformulation. This makes it particularly suitable for multiple cascaded resonators used in harmonic compensation systems. The technique has been validated using simulation and experimental investigations for a grid-connected inverter.