Axisymmetric structural optimization design and void control for selective laser melting

Additive manufacturing processes, of which Selective Laser Melting (SLM) is one, provide an increased design freedom and the ability to build structures directly from CAD models. There is a growing interest in using optimization methods to design structures in place of manual designs. Three design optimization problems were addressed in this paper. The first related to axisymmetric structures and the other two addressing important design constraints when manufacturing using SLM. These solutions were developed and applied to a case study of a turbine containment ring. Firstly, many structural components such as a turbine containment ring are axisymmetric while they are subjected to a non-axisymmetric load. A solution was presented in this paper to generate optimized axisymmetric designs for a problem in which the mechanical model was not axisymmetric. The solution also worked equally well for generating a prismatic geometry with a uniform cross section, requiring no change in the procedure from axisymmetric designs to achieve this. Secondly, the SLM process experiences difficulties manufacturing structures with internal voids larger than a certain upper limit. A method was developed that allowed the designer to provide a value for this upper limit to the optimization method which would prevent the generation of internal voids larger than this value in any optimized design. The method calculated the sizes of all the voids and did not increase their size once they reached this limit. It was also aware of voids near each other, providing a minimum distance between them. Finally, in order to remove the metal powder, that fills the internal voids of structures built using SLM to reduce unnecessary weight, a method was developed to build paths to join the internal voids created during the optimization process. It allowed the analyst to nominate suitable path entrance locations from which powder could be removed, then found the shortest path connecting all voids and these l