Power scalability in a mesh-connected reconfigurable architecture

We analyze power--area--performance trade-offs within a hypothetical mesh-connected reconfigurable architecture. A new analytic model relating area, power, and performance based on a simple VLSI complexity metric, is used to determine the behavior of some computing functions mapped to the platform. Although it might reasonably be expected that entirely local connectivity in the array would impose severe delay overheads, thus making performance--power trade-offs more difficult, it was found that the flexibility of the reconfigurable platform, in which logic and interconnect are (mostly) interchangeable, can result in compact layouts, which tends to offset the impact of the interconnect delay.